NTA UGC NET/JRF Exam, August -2024 (Electronic Science)

Total Questions: 100

21. A 6-bit DAC has a step size of 50 mV. The full-scale output voltage and percentage resolution for this will be:

Correct Answer: D. 3.15 V, 1.587%
Solution:A 6-bit DAC has 2⁶ = 64 discrete
levels. Its full-scale output voltage is
(2⁶ - 1) × (step size) = 63 × 50 mV  = 3.15 V
The percentage resolution is

22. The qutput of a control system is

c(t) = 1 + 0.25e⁻⁵⁰ᵗ - 1.25e⁻¹⁰ᵗ
For an unit step input, its undamped natural frequency and damping ratio will be:

Correct Answer: D. 22.36 rad/s & 1.34
Solution:

The given unit-step response is
c(t) = 1 + 0.25 e⁻⁵⁰ᵗ - 1.25 e⁻¹⁰ᵗ
Its two exponential terms e⁻⁵⁰ᵗ: and e⁻¹⁰ᵗ suggest system poles at 50 and 10. A standard second-order system has

23. The voltage gain for the given common source FET circuit is:

FET 2N5457 Parameters:

Correct Answer: B. -7.9

24. Arrange the following logic families in increasing order of their noise margin

(a) TTL (Transistor - Transistor Logic)
(b) ECL (Emitter Coupled Logic)
(c) MOS (Metal Oxide Semiconductor Logic)
(d) IIL (Integrated Injection Logic)

Correct Answer: A. (b), (d), (a), (c)
Solution:

Typical noise margins (smallest to largest) for the listed logic families are:
ECL < IIL < TTL < MOS
Hence in increasing order: (b), (d), (a), (c).

25. For single - phase full-wave firing pulse generator using, inverse cosine control principle, arrange the different sections of the circuit starting from input AC supply to the gate of the SCR

(a) Clock pulse generator
(b) Isolating transformer
(c) 90° phase shift circuit to obtain cosine timing wave
(d) Level comparator
(e) Pulse - output Flip Flop

Correct Answer: В. (с), (b), (d), (a), (e)
Solution:

For "inverse cosine" firing control of a single-phase full-wave trigger:
(c) A 90° phase-shift circuit produces the cosine-shaped reference.
(b) An isolating transformer is then used for safety and signal transfer.
(d) A level comparator compares the reference with a control level.
(a) A clock pulse generator provides timing pulses.
(e) A flip-flop shapes the final gate-drive pulses.

26. Match the List-I with List-II for 8051 microcontroller.

List-I (Timer mode)List-II (Operation)
(a) Mode 0I. 16-bit timer/counter
(b) Mode 1II. Two 8-bit timers using timer 0
(c) Mode 2III. 13 bit timer/counter
(d) Mode 3IV. Auto-reload of TL from TH

Choose the correct answer from the options given below:

(a)(b)(c)(d)
A.IIIIVIII
B.IIIVIIII
C.IIIIVIII
D.IIIIIVII
Correct Answer: D.
Solution:

For the 8051 timer modes:
(a) Mode 0 is the 13-bit timer/counter → III
(b) Mode 1 is the 16-bit timer/counter → І
(c) Mode 2 is 8-bit auto-reload → IV
(d) Mode 3 is the split-timer mode → II

27. For a standard telephone circuit with а signal-to-noise power ratio of 1000 and a BW of 2.7 KHz, the Shannon limit for Information capacity approximately is:

Correct Answer: A. 26.9 Kbps
Solution:

Shannon's capacity formula is:
C = B log₂ (1 + SNR)
For a 2.7 kHz channel (B = 2700 Hz) and SNR = 1000:
C≈ 2700 × log, (1001)
≈2700 × 9.97
≈ 26.9 Kbps.

28. Match the List-I with List-II.

List-I (Satellite Band)List-II (Uplink Frequency (GHz))
(a) C-BandI. 7.9 – 8.4
(b) X-BandII. 27 – 30
(c) Ku-BandIII. 5.9 – 6.4
(d) Ka-BandIV. 14 – 14.5

Choose the correct answer from the options given below:

(a)(b)(c)(d)
A.IIIIIVII
B.IIIIIIVI
C.IIIIIIIV
D.IIIVIIII
Correct Answer: A.
Solution:

(Typical Uplink Bands):
(a) C-Band: 5.9-6.4 GHz → II
(b) X-Band: 7.9-8.4 GHz →I
(c) Ku-Band: 14-14.5 GHz → IV
(d) Ka-Band: 27-30 GHz → II

29. Match the List-I with List-II that pertains to EEG signals and normal ECG wave patterns:

List-IList-II
(a) Gamma (ϒ)I. 0.12 – 0.2s
(b) Theta (θ)II. 0.05 – 0.10s
(c) QRS intervalIII. 4.8 Hz
(d) PR intervalIV. 22-30 Hz

Choose the correct answer from the options given below:

(a)(b)(c)(d)
A.IVIIIIII
B.IIIIVIII
C.IVIIIIII
D.IIIIVIII
Correct Answer: A.
Solution:Typical ranges:
(a) Gamma (ϒ) in EEG: about 22-30 Hz → IV
(b) Theta (θ) in EEG: about 4-8 Hz ≈ 4.8 Hz III
(c) QRS interval in ECG: about 0.05-0.10 s →II
(d) PR interval in ECG: about 0.12-0.20 s →I

30. For a super heterodyne receiver the correct sequence of block to receive a signal is:

(a) Mixer                        (b) RF stage
(c) Antenna                   (d) Detector
(e) IF Amplifier

Correct Answer: B. (c), (b), (a), (e), (d)
Solution:

(Superheterodyne Blocks): From antenna to output detector, the usual chain is:
(c) Antenna
(b) RF stage
(a) Mixer (to generate IF)
(e) IF amplifier
(d) Detector